High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• 83 base instructions with flexible addressing modes
• 24-bit wide instructions, 16-bit wide data path
• 12 Kbytes on-chip Flash program space
• 512 bytes on-chip data RAM
• 16 x 16-bit working register array
• Up to 30 MIPS operation: - Dual Internal RC - 9.7 and 14.55 MHz (±1%) Industrial Temp - 6.4 and 9.7 MHz (±1%) Extended Temp - 32X PLL with 480 MHz VCO - PLL inputs ±3% - External EC clock 6.0 to 14.55 MHz - HS Crystal mode 6.0 to 14.55 MHz
• 32 interrupt sources
• Three external interrupt sources
• 8 user-selectable priority levels for each interrupt






• 4 processor exceptions and software traps